1. Field of the Invention
The present invention relates to a bit error measurement circuit for evaluating a device such as an IC, a transmission device, a transmission line or the like. In particular, the present invention relates to a bit error measurement circuit which evaluates the above-described devices by using a test signal pattern set by a user arbitrarily.
2. Description of Related Art
In a bit error measurement, a test signal is transmitted by a transmitter and is received by a receiver through an object to be measured, e.g., a device such as an IC, a transmission device, a transmission line or the like. By carrying out a bit error measurement for the test signal received by a receiver, the measuring object is evaluated. In a pattern of the test signal, a pseudo-random pattern or a pattern set by a user arbitrarily is used frequently.
A transmitter transmits the test signal having the above-described pattern periodically and repeatedly. A receiver receives the test signal transmitted by a transmitter and memorizes one period of the test signal in a memory thereof by a pull-in operation, so that a reference signal is generated in a receiver. The following test signal transmitted by a transmitter is considered as a signal to be measured, and thereafter each bit of the signal to be measured is compared with that of the reference signal. As a result, bit errors are detected and are counted, so that a bit error rate is calculated.
In such a conventional bit error measurement circuit, for example, Japanese Patent Publication (Unexamined) No. Tokukai-Hei 8-149112 discloses a bit error measurement circuit. The conventional bit error measurement circuit will be explained in detail hereinbelow with reference to FIGS. 6 to 9.
FIG. 6 is a block diagram showing a composition of a conventional bit error measurement circuit 200.
FIG. 7 is a block diagram showing a composition of a memory circuit 20 shown in FIG. 6.
The compositions of the bit error measurement circuit 200 and of the memory circuit 20 will be explained.
In FIG. 6, the bit error measurement circuit 200 comprises the memory circuit 20, an address counter 30, a switching circuit 40, an error detection circuit 50, a gate circuit 51, an error counter 60 and a clock counter 70. Further, in FIG. 6, reference numeral 1 denotes an input terminal for a signal to be measured (a test signal) 1a, 2 denotes an input terminal for a clock signal 2a, 3 denotes an input terminal for a maximum address number 3a of the address counter 30, 4 denotes an input terminal for an address counter control signal 4a, 5 denotes an input terminal for a pull-in signal 5a, 31 denotes an output terminal for an address carry-up signal 30b, 61 denotes an output terminal for a counted number 60a of errors and 71 denotes an output terminal for a counted number 70a of clock pulses.
In FIG. 7, the memory circuit 20 comprises two data input-output terminals 20X and 20Y, an address input terminal 20A, a read-write control signal input terminal 20RW and a switching signal input terminal 20SW as external terminals. Further, the memory circuit 20 comprises a memory 201 and a switching circuit 202 therein. The memory 201 has a data input-output terminal 201D, an address input terminal 201A and a read-write control signal input terminal 201RW. The switching circuit 202 has two switching terminals 202X and 202Y, a common terminal 202Z and a switching signal input terminal 202SW.
One switching terminal 202X of the switching circuit 202 is connected with the data input-output terminal 2 OX of the memory circuit 20. The other switching terminal 202Y is connected with the data input-output terminal 20Y of the memory circuit 20. The common terminal 202Z is connected with the data input-output terminal 201D. The switching signal input terminal 202SW is connected with the switching signal input terminal 20SW of the memory circuit 20. The address input terminal 201A of the memory 201 is connected with the address input terminal 20A of the memory circuit 20. The read-write control signal input terminal 201RW is connected with the read-write control signal input terminal 20RW of the memory circuit 20.
In FIG. 6, the signal 1a to be measured, which is inputted into the terminal 1 is inputted to a data input-output terminal 20X. The address number 30a outputted from an address output terminal 30OUT of the address counter 30 is inputted to the address input terminal 20A. The read-write control signal 40a outputted from an output terminal 40OUT of the switching circuit 40 is inputted to the read-write control signal input terminal 20RW. The pull-in signal 5a inputted into the terminal 5 is inputted to the switching signal input terminal 20SW.
When a logic value of the pull-in signal 5a inputted to the switching signal input terminal 20SW is "0", that is, when the pull-in operation is carried out, the switching circuit 202 of the inside of the memory circuit 20 shown in FIG. 7 connects the common terminal 202Z with the switching terminal 202X. As a result, the signal 1a to be measured, which is inputted into the data input-output terminal 20X is read and is written to the address which is indicated by the address number 30a inputted into the address input terminal 20A, by the rise of the read-write control signal 40a.
When a logic value of the pull-in signal 5a inputted to the switching signal input terminal 20SW is "1", that is, when the pull-in operation is not carried out, the switching circuit 202 of the inside of the memory circuit 20 shown in FIG. 7 connects the common terminal 202Z with the switching terminal 202Y. As a result, the data of the address which is indicated by the address number 30a inputted into the address input terminal 20A is read and is outputted from the data input-output terminal 20Y to one input terminal 50IB of the error detection circuit 50 as a reference signal 20a.
The address counter 30 comprises a clock terminal 30CLK, a maximum address number input terminal 30AM, a reset terminal 30RST, a carry-up signal output terminal 30C and an output terminal 30OUT. The clock signal 2a inputted into the terminal 2 is inputted to the clock terminal 30CLK. The maximum address number 3a inputted into the terminal 3 is inputted to the maximum address number input terminal 30AM. The address counter control signal 4a inputted into the terminal 4 is inputted to the reset terminal 30RST.
When a logic value of the address counter control signal 4a inputted to the reset terminal 30RST is "1", that is, when the count operation is carried out, the address counter 30 carries out the count-up operation by the clock signal 2a inputted to the clock terminal 30CLK and outputs the counted number from the output terminal 30OUT to the address input terminal 20A of the memory circuit 20 as an address number 30a. The counted number reaches the maximum address number 3a inputted into the maximum address number input terminal 30AM, so that the counted number is reset. At the same time, a pulse signal is outputted from the carry-up signal output terminal 30C to the terminal 31 as an address carry-up signal 30b and the count operation is carried out again.
When a logic value of the address counter control signal 4a inputted to the reset terminal 30RST is "0", that is, when the reset operation is carried out, the address counter 30 resets the counted number.
The switching circuit 40 comprises a data input terminal 40X, a data input terminal 40Y, a switching signal input terminal 40SW and an output terminal 40OUT. The clock signal 2a inputted into the terminal 2 is inputted to the data input terminal 40X. A signal having a logic value "1" (High-level signal "H") is inputted to the data input terminal 40Y. The pull-in signal 5a inputted into the terminal 5 is inputted to the switching signal input terminal 40SW.
When a logic value of the pull-in signal 5a inputted to the switching signal input terminal 40SW is "0", that is, when the pull-in operation is carried out, the output terminal 40OUT is connected with the data input terminal 40X in the switching circuit 40, so that the clock signal 2a inputted into the data input terminal 40X is outputted from the output terminal 40OUT to the read-write control signal input terminal 20RW of the memory circuit 20 as a read-write control signal 40a.
When a logic value of the pull-in signal 5a inputted to the switching signal input terminal 40SW is "1", that is, when the pull-in operation is not carried out, the output terminal 40OUT is connected with the data input terminal 40Y in the switching circuit 40, so that the signal having the logic value "1" (High-level signal "H") is outputted from the output terminal 40OUT of the switching circuit 40 to the read-write control signal input terminal 20RW of the memory circuit 20 as a read-write control signal 40a.
The error detection circuit 50 comprises a data input terminal 50IA, a data input terminal 50IB and an output terminal 50OUT. The signal 1a to be measured, which is inputted into the terminal 1 is inputted to the data input terminal 50IA. The reference signal 20a outputted from the data input-output terminal 20Y of the memory circuit 20 is inputted to the data input terminal 50IB.
The error detection circuit 50 compares the signal 1a to be measured, which is inputted into the data input terminal 50IA with the reference signal 20a inputted into the data input terminal 50IB. When it is detected that a bit of the signal 1a to be measured is different from that of the reference signal 20a, that is, when a bit error is detected, a signal having a logic value "1"0 is outputted from the output terminal 50OUT to the data input terminal 51IA of the gate circuit 51 as an error detection signal 50a. When it is detected that a bit of the signal 1a to be measured is the same as that of the reference signal 20a, that is, when a bit error is not detected, a signal having a logic value "0" is outputted from the output terminal 50OUT to the data input terminal 51IA of the gate circuit 51 as an error detection signal 50a.
The gate circuit 51 comprises a data input terminal 51IA, a data input terminal 51IB and an output terminal 510UT. The error detection signal 50a outputted from the output terminal 50OUT of the error detection circuit 50 is inputted to the data input terminal 51IA. The clock signal 2a inputted into the terminal 2 is inputted to the data input terminal 51IB.
The gate circuit 51 outputs a signal having a logic value "1" from the output terminal 51OUT to the clock terminal 60CLK of the error counter 60 when both a logic value of the error detection signal 50a inputted into the data input terminal 51IA and that of the clock signal 2a inputted into the data input terminal 51IB are "1". That is, the result of AND operation of the error detection signal 50a and the clock signal 2a is outputted from the output terminal 51OUT to the clock terminal 60CLK of the error counter 60 as an error detection pulse signal 51a.
The error counter 60 comprises a clock terminal 60CLK, a reset terminal 60RST and an output terminal 60OUT. The error detection pulse signal 51a outputted from the output terminal 51OUT of the gate circuit 51 is inputted to the clock terminal 60CLK. The pull-in signal 5a inputted into the terminal 5 is inputted to the reset terminal 60RST.
When a logic value of the pull-in signal 5a inputted to the reset terminal 60RST is "0", that is, when the pull-in operation is carried out, the error counter 60 resets the counted number of the bit errors.
When a logic value of the pull-in signal 5a inputted to the reset terminal 60RST is "1", that is, when the pull-in operation is not carried out, the error counter 60 counts up the bit errors by inputting the error detection pulse signal 51a into the clock terminal 60CLK and outputs the counted number from the terminal 61 to the outside of the bit error measurement circuit as a counted number 60a of errors.
The clock counter 70 comprises a clock terminal 70CLK, a reset terminal 70CLK and an output terminal 70OUT. The clock signal 2a inputted into the terminal 2 is inputted to the clock terminal 70CLK. The pull-in signal 5a inputted into the terminal 5 is inputted to the reset terminal 70RST.
When a logic value of the pull-in signal 5a inputted to the reset terminal 70RST is "0", that is, when the pull-in operation is carried out, the clock counter 70 resets the counted number of clock pulses.
When a logic value of the pull-in signal 5a inputted to the reset terminal 70RST is "1", that is, when the pull-in operation is not carried out, the clock counter 70 counts up the pulses by inputting the clock signal 2a to the clock terminal 70CLK and outputs the counted number from the terminal 71 to the outside of the bit error measurement circuit as a counted number 70a of clock pulses.
The operation of the bit error measurement 200 shown in FIG. 6 will be explained with reference to a time chart shown in FIG. 8.
In FIG. 8, the reference numeral 2a denotes a waveform illustration showing the clock signal.
The reference numeral 1a denotes a waveform illustration showing the signal to be measured. In this case, the length of one period is 6 bits. The marks A to F and the periodic number denote each bit of the signal to be measured. For example, each bit of the first period is denoted by the marks D1, E1, F1, A1, B1 and C1, each bit of the second period is denoted by the marks D2, E2, F2, A2, B2 and C2, and the like. As shown in FIG. 8, the period is from the first bit written in the memory circuit 20 to the last bit done. Therefore, the period is not necessarily coincident with a period which is determined on the basis of the first bit and the last bit of the pattern set by a transmission device.
A line attached to the upper position of the mark indicates an erroneous bit. For example, because a line is attached to the upper position of the mark A3, the bit A3 is an erroneous bit.
The reference numeral 3a denotes a signal setting the maximum address number of the address counter 30. As shown in FIG. 8, because the length of one period of the signal to be measured is 6 bits, the maximum address number 3a is "6".
The reference numeral 4a denotes a waveform illustration showing the address counter control signal. As shown in FIG. 8, when the logic value of the address counter control circuit 4a is "0", the address counter 30 is reset. The reference numeral 30a denotes a waveform illustration showing the address number outputted by the address counter 30, 30b denotes a waveform illustration showing the address carry-up signal outputted by the address counter 30.
The reference numeral 5a denotes a waveform illustration showing the pull-in signal. As shown in FIG. 8, when the logic value of the pull-in signal 5a is "0", the pull-in operation is carried out. The error counter 60 and the clock counter 70 are operated by the pull-in signal 5a. When the logic value of the pull-in signal 5a is "1", that is, when the pull-in operation is not carried out, the error counter 60 and the clock counter 70 carry out the count operation. When the logic value of the pull-in signal 5a is "0", that is, when the pull-in operation is carried out, each number counted by the two counters is reset and each count operation is stopped.
The reference numeral 40a denotes a waveform illustration showing the read-write control signal of the memory 201, 20a denotes a waveform illustration showing the error detection reference signal outputted by the memory circuit 20, 50a denotes a waveform illustration showing the error detection signal, 51a denotes a waveform illustration showing the error detection pulse signal, 60a denotes a waveform illustration showing the counted number of errors and 70a denotes a waveform illustration showing the counted number of clock pulses.
At the time t1, a signal having a logic value "0" is inputted to the reset terminal 30RST of the address counter 30 by converting the logic value "1" of the address counter control signal 4a inputted to the terminal 4 into the logic value "0", so that the address number 30a of the address counter 30 is reset. At the same time that the reset operation is carried out by the address counter control signal 4a, the logic value "1" of the pull-in signal 5a inputted to the terminal 5 is converted into the logic value "0", that is, the pull-in operation of the signal 1a to be measured is carried out.
A signal having a logic value "0" is inputted to the switching signal input terminal 40SW of the switching circuit 40 by the logic value "0" of the pull-in signal 5a, so that the output terminal 40OUT of the switching circuit 40 is connected with the data input terminal 40X in the switching circuit 40. At the same time, the clock signal 2a inputted into the data input terminal 40X is outputted to the read-write control signal input terminal 20RW of the memory circuit 20 as a read-write control signal 40a.
A signal having a logic value "0" is inputted to the switching signal input terminal 20SW of the memory circuit 20 by the logic value "0" of the pull-in signal 5a, so that the switching circuit 202 of the inside of the memory circuit 20 connects the switching terminal 202X with the common terminal 202Z. At the same time, the signal 1a to be measured, which is inputted into the data input-output terminal 20X is inputted to the data input-output terminal 201D of the memory 201.
A signal having a logic value "0" is inputted to the reset terminal 60RST of the error counter 60 and to the reset terminal 70RST of the clock counter 70 by the logic value "0" of the pull-in signal 5a, so that the counted number 60a of errors and the counted number 70a of clock pulses are reset and each count operation is stopped.
At the time t2, a signal having a logic value "1" is inputted to the reset terminal 30RST of the address counter 30 by converting the logic value "0" of the address counter control signal 4a into the logic value "1", and the reset operation of the address counter 30 is canceled, so that the address counter 30 carries out the count-up operation by inputting the clock signal 2a into the clock terminal 30CLK and outputs the address number 30a counted by the address counter 30 from the output terminal 30OUT to the address input terminal 20A of the memory circuit 20.
Because of the rise of the read-write control signal 40a inputted to the read-write control signal input terminal 20RW of the memory circuit 20 at the time t2, the memory circuit 20 writes the bit D1 of the signal 1a to be measured, which is inputted to the data input-output terminal 20X at the time t2 to the address "1" of the memory 201, which is indicated by the address number 30a inputted into the address input terminal 20A by the address counter 30.
Subsequently, before the address number 30a counted by the address counter 30 reaches the maximum address number 3a (=6) and the address counter 30 carries up, the bits E1, F1, A1 . . . of the signal 1a to be measured are read and are written in the memory 201.
At the time t3, the address counter 30 counts up to the address number defined by the maximum address number 3a, so that the address carry-up pulse P1 is outputted from the carry-up signal output terminal 30C as an address carry-up signal 30b. At the same time that the address carry-up pulse P1 rises, a logic value of the pull-in signal 5a becomes "1".
A signal having a logic value "1" is inputted to the switching signal input terminal 40SW of the switching circuit 40 by the logic value "1" of the pull-in signal 5a, so that the output terminal 40OUT of the switching circuit 40 is connected with the data input terminal 40Y in the switching circuit 40. At the same time, a signal having a logic value "1" (High-level signal "H") inputted into the data input terminal 40Y is outputted from the output terminal 40OUT to the read-write control signal input terminal 20RW of the memory circuit 20 as a read-write control signal 40a. Because a signal fixed at a logic value "1" is inputted to the read-write control signal input terminal 20RW, the memory circuit 20 is fixed in the mode that the data memorized in the memory 201 are read out.
A signal having a logic value "1" is inputted to the switching signal input terminal 20SW of the switching circuit 20 by the logic value "1" of the pull-in signal 5a, so that the switching circuit 202 of the inside of the memory circuit 20 connects the switching terminal 202Y with the common terminal 202Z. At the same time, the memory circuit 20 reads the data written to the address of the memory 201, which is indicated by the address number 30a inputted to the address input terminal 20A at the time t3 by the address counter 30, and outputs the data from the data input-output terminal 20Y.
Subsequently, the memory circuit 20 reads the data written in the memory 202 similarly to the above-described method. As shown in FIG. 8, the bits D1, E1, F1, A1, B1 and C1 are written in the memory circuit 20 from the time t2 to the time t3, and are read periodically and repeatedly.
A signal having a logic value "1" is inputted to the reset terminal 60RST of the error counter 60 and to the reset terminal 70RST of the clock counter 70 by the logic value "1" of the pull-in signal 5a, so that the reset operations of the error counter 60 and the clock counter 70 are canceled and each counter carries out the count-up operation. Subsequently, the clock counter 70 counts the bits measured for a bit error indirectly as a counted number 70a of clock pulses by counting the pulses of the clock signal 2a.
At the time t4, the erroneous bit E2 of the signal 1a to be measured is inputted to the data input terminal 50IA of the error detection circuit 50. Similarly, the correct bit E1 of the reference signal 20a is inputted from the memory circuit 20 to the data input terminal 50IB of the error detection circuit 50. As a result, the error detection circuit 50 outputs an error detection pulse P2 from the output terminal 50OUT as an error detection signal 50a. The error detection pulse P2 is inputted to the data input terminal 51IA of the gate circuit 51 as an error detection signal 50a, so that the result of AND operation of the error detection signal 50a and the clock signal 2a inputted into the data input terminal 51IB is outputted from the output terminal 510UT to the clock terminal 60CLK of the error counter 60 as an error detection pulse signal 51a. The error detection pulse signal 51a is the same waveform as the clock signal 2a while the logic value of the error detection signal 50a is "1".
The error counter 60 counts up the counted number 60a of errors by inputting the error detection pulse signal 51a from the gate circuit 51 to the clock terminal 60CLK.
Subsequently, by the similar operation, the error counter 60 counts the erroneous bits. The bit error rate is calculated by dividing the counted number of errors 60 counted by the error counter 60 by the counted number 70a of clock pulses.
The conventional bit error measurement circuit 200 ensures that the pull-in operation is carried out for transmission time of one periodic data and the signal to be measured is synchronized with the reference signal. However, because the data fed into the memory 201 as a reference signal 20a is not measured for a bit error, there is a problem that a bit error measurement cannot be carried out precisely if the reference signal 20a has a bit error.
FIG. 9 is a time chart showing the example of the above-described problem. In FIG. 9, because the reference numerals denoting the signals are the same as those of FIG. 8, the explanations of the numerals are omitted. Further, in FIG. 9, the positions of the bit errors inputted after the second period of the signal 1a to be measured are the same as those shown in FIG. 8. However, FIGS. 8 and 9 are different in the point whether the bit A1 of the first period is erroneous or not.
At the time t3, because the memory circuit 20 writes the erroneous bit A1 as a reference signal, the reference signal 20a outputted from the data input-output terminal 20Y of the memory circuit 20 to the error detection circuit 50 includes the erroneous bit A1.
At the time t6, however the bit A2 of the signal 1a to be measured, which is inputted into the data input terminal 50IA of the error detection circuit 50 is a correct bit, an error detection pulse P3 is outputted from the output terminal 50OUT as an error detection signal 50a because of the erroneous bit A1 of the reference signal 20a inputted into the data input terminal 50IB.
On the other hand, at the time t7, however the erroneous bit A3 of the signal 1a to be measured is inputted into the data input terminal 50IA of the error detection circuit 50, because of the erroneous bit A1 of the reference signal 20a inputted into the data input terminal 50IB, the two signals inputted into the data input terminal 50IA and the data input terminal 50IB are same. As a result, the error detection circuit 50 does not generate the error detection pulse.
As described above, in the case that the data used as a reference signal has an erroneous bit, the bit error measurement cannot be carried out precisely. In particular, because the bit error which necessarily occurs at the same bit of each period cannot be detected, there is a problem that a serious defect of measuring objects, such as a logical miss, cannot be detected.